SlimBridgeController()

template<int DATA_PIN, typename TIMING, EOrder RGB_ORDER, int WAIT_TIME, typename DriverTraits, int XTRA0 = 0, bool DIRECT_SHOW = (FL_SLIM_BRIDGE_DIRECT_SHOW != 0)>

fl::SlimBridgeController< DATA_PIN, TIMING, RGB_ORDER, WAIT_TIME, DriverTraits, XTRA0, DIRECT_SHOW >::SlimBridgeController ( )

inline

Definition at line 108 of file slim_bridge_controller.h.

                                        {
        ChipsetTimingConfig timing = makeTimingConfig<TIMING>();
        // (A?) Fold WAIT_TIME (microseconds) into reset_us, mirroring the
        // historical ClocklessIdf4 behavior: the driver must honor whichever
        // is longer -- the chipset's own latch/reset requirement, or the
        // caller-requested minimum inter-frame wait.
        if (WAIT_TIME > 0 && static_cast<u32>(WAIT_TIME) > timing.reset_us) {
            timing.reset_us = static_cast<u32>(WAIT_TIME);
        }
        // A clockless controller bound to a unified parallel-IO bus needs
        // that engine's clockless pipeline linked (#4793).
        detail::enable_clockless<DriverTraits>();
        mData = ChannelData::create(DATA_PIN, timing, fl::vector_psram<u8>(),
                                     ChannelPixelFormat::RGB);
        FL_STATIC_ASSERT(XTRA0 >= 0 && XTRA0 <= 32, "XTRA0 out of range");
        mData->setExtraZeroBitsPerByte(static_cast<u8>(XTRA0));
        // Idempotent by contract -- safe to call from every instantiation's
        // constructor (mirrors ClocklessIdf5's registerWithManager() call).
        // A no-op in direct-show mode.
        Policy::template attach<DriverTraits>();
    }

References fl::ChannelData::create(), DATA_PIN, fl::detail::enable_clockless(), fl::FL_NO_EXCEPT, FL_STATIC_ASSERT, fl::makeTimingConfig(), mData, fl::ChipsetTimingConfig::reset_us, and fl::RGB.

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